1. Field of the Invention:
The present invention relates to a digital data processor, more specifically, the invention relates to a data processor which effects pipeline processing and which features an increased computing speed as a whole.
Pipeline processing, in general, serves as an effective instruction control system from the standpoint of increasing computing speed. The present invention is concerned with a data processor relying upon a pipeline control system which works even when there is a great difference between the time taken for reading an instruction and the time taken for executing an operation.
2. Description of the Prior Art:
A data processor decodes an instruction word which has been read out, reads data according to the decoded contents, and executes an operation. The operation is processed using the pipeline control system, and the next microinstruction is read out in parallel with the processing of the operation. In this case, when the time required for reading a microinstruction is the same as the time required for executing an operation, the time is regarded as the microcycle period and no inconvenience results. Usually, however, the two times are not the same. In practice, the microcycle period (machine cycle) is based upon the longer one as the reference. That is, despite the use of a pipeline control system, the overall operating efficiency is not improved.
A pipeline processing system has been disclosed in U.S. Pat. No. 3,978,452 entitled "System and Method for Concurrent and Pipeline Processing Employing a Data Driven Network". The above patent discloses local storage in a data-driven network processor but does not in any way refer to problems inherent in the conventional art.